Forum - Disagreement between NEC Compiler and Assembly language manual and other assembly related problems

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[#114]

On page 32 of Assembly language manual the comments for the instruction VFMS reads

If cf is “af” or “at”, %vz can be omitted. If cf is “at”, cf can be omitted.

However when i had access to the NEC compiler is rejects inline assembly with an optional .at on the HLRS system. It acts like the manual should say:

If cf is “af” or “at”, %vz must be omitted.

I no longer have access to the HLRS system.

Posted by Johann-Tobias Schäg on 26 December 2022 at 16:03.
Edited by Johann-Tobias Schäg on 6 April 2023 at 22:33.

Sorry for the late answer.

Thank you for pointing this out.
This is an error in the manual.
As you pointed out, if cf is "af" or "at", %vz cannot be specified.
We will correct it in the next version of the manual.

Posted by NEC SDK team (forum administrator) on 31 January 2023 at 07:34.
Edited by NEC SDK team (forum administrator) on 31 January 2023 at 07:35.

I noticed that on page 109 of the SX-Aurora TSUBASA C/C++ Compiler User’s Guide the Example for an Extended Asm Statement appears wonky to me on Firefox, Chrome, Edge on Windows and Linux. The underlying text when copy and pasted seems to be normal though. This might related to locale issues which are outside my expertise.

Screenshot of SX-Aurora TSUBASA C-C++ Compiler User’s Guid.png

Another problem i noticed is that some instructions have a p- variant fro example vrsqrt and pvrsqrt . As per the ISA Guide there are 4 variants of vrsqrt. Compute it of a 64 bit float, a 32 bit float in the upper half, a 32 bit float in the lower half or for two 32 bits floats. Based on cardfull reading of the ISA guide and the VectorEngine as manual i could not figure out what the difference of vrsqrt.w and pvrsqrt are the same or what distinguishes them.

I could not find any documentation on the LLVM intrinsics.

Posted by Johann-Tobias Schäg on 6 April 2023 at 23:04.

Further comments on the C/C++ language guide. (I can't seem to edit my own posts).

There is no example for making inline assembly with vector operations. Given that this is the most performance relevant type of operation that seems like an oversight.

It is not clear how to exchange vector masks between inline assembly and normal C/C++ code. It is not clear how to incidacte that assembly code changed the vector length register.

The use of quad precision numbers in C/C++ and in so far it is even possible their use in inline assembly could be explained. All constraint types in inline assembly should be demonstrated in examples. It is especially unclear how to use # and *.

I think the discussion of LLVM intrinsics and other dicussions of the open source or community compilers could be better served in a seperate "(with OSS)" document. I understand that given the introduction of a new model of VectorEngine and other concerns is not a priority. If i have collected enough material at some point i might start a thread on the forum or a GitHub repo.

Posted by Johann-Tobias Schäg on 7 April 2023 at 17:03.

According to

Screenshot 2023-05-10 015232.png

and

Screenshot 2023-04-06 224628.png

I would expect the code asm("vfadd.h %v5, %v6, %v7"); to compile but invoking it with /opt/nec/ve/bin/ncc-5.0.0 -march=ve3 resjlts in a /tmp/nccGcRpaa.s: Assembler messages: /tmp/nccGcRpaa.s:3: Error: Invalid assembler mnemonic 'vfadd.h'.

Posted by Johann-Tobias Schäg on 10 May 2023 at 00:02.